This invention relates to solid-state imager arrangements and more particularly to arrangements in which signal charge multiplication is implemented.
In a typical charge coupled device (CCD) imager, signal charge representative of incident radiation is accumulated in an array of pixels over an image area. Following an integration period, signal charge is transferred to an output register by applying appropriate clocking or drive pulses to control electrodes. The signal charge is then read out from the output register and applied to a charge detection circuit to produce a voltage, which is representative of the amount of signal charge.
Our previously published patent application, GB-A-2323471 discloses a CCD imager arrangement in which signal charge multiplication is obtained by providing a separate multiplication register following the output register. Charge is transferred through high field regions in elements of the multiplication register, thus accelerating the signal charge carriers and generating additional carriers through impact ionisation. As carrier multiplication occurs outside the conventional CCD structure itself, both the operation of the multiplication register and the CCD imager may be optimised without compromising the performance of one for the sake of the other.
The present invention seeks to provide an improved solid-state imager arrangement.